1. Technical Field
The present disclosure relates to a synchronization detecting apparatus and, more particularly to an apparatus for detecting the length of a line and detecting synchronization information based on the detected length of the line.
2. Discussion of Related Art
Various kinds of electronic devices include a video signal processor that processes an input analog video signal. For example, optical disk players, such as a digital versatile disk (DVD) player, and display systems, such as a video cassette recorder (VCR), a television (TV), and a personal computer (PC), include a video signal processor.
A video consists of a time-ordered sequence of images. Each image in the sequence is referred to as a frame. Different techniques are available to render the video, such as interlaced scanning.
In an interlaced scan method, each video frame is composed of two interlaced fields. Each of the fields consists of a plurality of scan lines or simply “lines” that make up an image. One of the two fields consists of odd-numbered scan lines, and the other field consists of even-numbered lines. The field that contains the first scan line from the top is called the upper or top field, and the other field is called the lower or bottom field.
A vertical synchronization (VSYNC) signal indicates timing information such as the beginning of a field. A horizontal synchronization (HSYNC) signal indicates timing information such as the beginning of a scan line.
An analog video signal supplied to a video signal processor may be a composite video blanking synchronization (CVBS) signal, a separate (S)-video signal, or a component signal.
The CVBS signal may be received via a tuner of a video signal processor such as a TV system. The S-video signal contains a luminance (Y) signal and a chrominance (C), signal and may be supplied to a video signal processor such as a VCR. The component signal contains a luminance (Y) signal and chrominance (Cb and Cr) signals (also called color difference signals Cb and Cr) and may be supplied to a video signal processor such as a DVD player.
FIG. 1 is a timing diagram of a CVBS signal 100 that is an example of an input video signal IVS supplied to a conventional video signal processor. When the analog video signal IVS supplied to a video signal processor is a CVBS signal, the video signal processor detects a synchronization signal and separates a luminance signal and a chrominance signal from the analog video signal IVS based on the synchronization signal.
However, in the case of an S-video signal or a component signal, the video signal processor need not separate the luminance signal from the chrominance signal because the luminance signal and the chrominance signal are transmitted separately in the S-video signal or the component signal transmission.
The video signal processor interpolates the luminance signal and the chrominance signal to generate a color signal that satisfies the standards of a display device, such as a liquid crystal display (LCD). The video signal processor may generate Red (R) Green (G) and Blue (B) video signals, or a color signal containing a luminance (Y) signal and chrominance (Cb and Cr) signals according to the display device standards. The generated color signal is displayed such that a user can view images on the display device.
Referring to FIG. 1, the CVBS signal 100 is comprised of a front porch signal 110, a horizontal synchronization pulse signal 130, a back porch signal 150 that contains a color burst signal 170, and an active video signal 190.
In a National Television System Committee (NTSC) method, the CVBS signal 100 includes 525 lines, each field consists of 262.5 lines and each line consists of 858 samples. In a phase alternating line (PAL) method, each line consists of 864 samples.
Each scan line of the CVBS signal 100 starts from a falling edge FE of the horizontal synchronization pulse signal 130 and ends at a falling edge FE of a next horizontal synchronization pulse signal 130.
The front porch signal 110 and the back porch signal 150 have a DC voltage level being referred to as a blank level BL, for example, 0 volts. The horizontal synchronization pulse signal 130 has a DC voltage level referred to as a sync level SL. A falling edge FE and a rising edge RE of the horizontal synchronization pulse signal 130 may be determined according to a DC threshold level TL. For example, the DC threshold level TL may be indicated as 50% of the amplitude of the horizontal synchronization pulse signal 130. The amplitude of the horizontal synchronization pulse signal 130 is equal to the absolute value of the difference between the blank level BL and a synchronization level SL.
A conventional method of detecting a horizontal synchronization signal and a vertical synchronization signal from the CVBS signal 100 will now be described with reference to FIG. 1. First, a blank level BL and a synchronization level SL are detected, and a threshold level TL is determined based on the detected blank level BL and the synchronization level SL. Falling edges FE or rising edges RE of the horizontal synchronization pulse signal 130 are detected based on the determined threshold level TL. A horizontal synchronization signal containing location information (time information) of the horizontal synchronization pulse signal 130 is detected using the difference between the detected falling edges FE (or the detected rising edges RE). A vertical synchronization signal may be detected by counting the detected horizontal synchronization signal to one-half the number of lines of the CVBS signal 100.
However, when the blank level BL and the synchronization level SL are changed due to noise, or a falling edge FE (or a rising edge RE) of the horizontal synchronization pulse signal 130 is deformed due to noise, the horizontal and vertical synchronization signals may not be correctly detected using the conventional method.